module main(
input CLK,
input A,
input RESET,
output reg[3:0] Y);
endmodule
For this problem you need Y to output 0 when a high RESET signal is received (at a rising clock edge), otherwise if A is high, then for every rising clock edge you must increment the output of 4 bit counter Y. when both RESET and A are low, Y should remain unchanged. You may use the plus operator and conditionals on this problem.
module main(
input CLK,
input A,
input RESET,
output reg[3:0] Y);
endmodule